Sub-task #	Work package(s)
ST1	Front-end electronics hardware and firmware 2 channel-wise self-triggered, very-high rate ASIC versions with ns time stamp and amplitude readout: 128-channel version for Si-MSD and CASCADE (N-XYTER) 32-channel version with variable gain for MSGC (MSGCROC) 3 detector specific ASIC boards 3 clock distribution boards 3 sets of ADC/FPGA front-end boards with 1-Gigabit readout interface VHDL firmware
ST2	Data Acquisition (DAQ) hardware and software Two quad-core 64-bit data acquisition CPUs with shared 8 Giga-Byte of memory (RAM) and an 8 Terra-Byte array of disks (RAID) Modular, 4-layer software system